Efficient representation and manipulation of numbers in computer systems presents many challenges for computer scientists and mathematicians. The goal of this art is to find a internal computer representation of numbers that:                Makes efficient use of computer storage (stores the numbers in as few bits as possible.)        Permits easy conversion to numbers for other operations (e.g., ASCII for display to users).        Permits fast numerical computation.To reconcile these goals, some computers and devices adopt the binary-coded decimal (“BCD”) representation. A BCD representation stores two decimal digits in a binary byte (8 binary bits). Each byte in the BCD representation is broken down into two groups of four bits. One decimal digit may be represented in each group of four bits. Thus, a 10 digit decimal number requires five bytes of storage in the BCD format.        
One of the particularly attractive features of the BCD format is the ability to convert BCD numbers to decimal numbers. Since each BCD number represents discrete decimal digits (one digit in four bits), it is relatively simple to determine the value of each group of four binary bits to determine the decimal number of the corresponding decimal digit.
Despite widespread adoption of this representation, microprocessor manufacturers have been slow to formally adopt the BCD representation. BCD manipulations have thus largely been performed in software, as opposed to hardware. What prevents manufacturers from including BCD manipulation hardware in their processors is the lack of a formalized standard for representing floating point numbers in BCD form. Following the codification of a standard, the software manufacturers and database manufacturers can make greater investments in such a format. With widespread adoption comes investment from microprocessor manufacturers in the BCD format.
The emergence of the IEEE 754R representation (“754R”) addresses the standardization of BCD floating point numbers. At the time of this writing, 754R has reached the final stages of standardization. In the near future, it is predicted that virtually all computer manipulations will be performed in the 754R format. Of course, there will be considerable latency between the time that IEEE 754R is ratified and the time that hardware support for this standard is commercially available. Current microprocessors do not possess hardware support for this new standard.
Without dedicated hardware support, 754R presents significant challenges to processor manufacturers and software developers who require specific types of calculations to be fast. For example, it is computationally expensive to compare two 754R values to determine which value has the greater or lesser value. Database queries, which are required to return their responses in an exceptionally short amount of time, cannot afford to absorb the additional processing time needed to manipulate numbers stored in the 754R format. Similarly, data sort operations are extremely expensive. Without sortability in database systems, 754R numbers may also be unable to serve as key fields in tables without implementing expensive software operations to convert the 754R numbers to a sortable format. Thus, there is a need in the art to provide a mechanism for legacy microprocessors and the like to process data in the 754R format but also provide for fast data comparison operations.